1. Field of the Invention
The present invention relates generally to the field of semiconductor device manufacturing. More particularly, the present invention relates to a method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning technique.
2. Description of the Prior Art
The tremendous growth of the semiconductor industry has been achieved by reducing the cost per function of integrated circuits. The semiconductor industry has kept on the historic productivity curve by improving equipment performance, throughput, and uptime; by improving manufacturing yield and efficiency; by improving product quality and reliability; and by increasing wafer size. The most significant contributor to keeping on the historic productivity curve has been by reducing integrated circuit feature sizes through advances in lithography. Reduction in feature sizes allows semiconductor manufacturers to fabricate more devices per wafer, reduce the size (hence the cost) per device, and increase the performance of each device. These advances translate into consumer benefits through electronic products that are smaller, cheaper, and superior in performance.
However, as the semiconductor technology advances to 50 nm node or beyond, for example, it is required to combine extra resolution enhancing techniques such as immersion lithography techniques and/or double patterning techniques in order to fabricate fine pattern of ultra-high density semiconductor devices with feature of 50 nm or less and to elongate the life of today's mainstream 193 nm optical lithography systems.
As known in the art, optical lithography systems are used to remove individual parts of a thin film or substrate. The system transfers a pattern from a photo mask to a photoresist using light. Chemicals are then used to etch the pattern in, beneath the photoresist. To prepare for this process, the wafer may be heated in order to remove the excess moisture from the wafer surface.
A photoresist is then applied through spin coating. Once it is reheated or baked, driving away any lingering solvent, the resist is then exposed to the light pattern. This exposes the basic pattern to the resist and then allows it to be etched on using a chemical agent. The photoresist can then be removed with the use of a resist stripper. The printing systems used for this process require a mask that lets in some light while keeping out other rays, creating a specific pattern. This type of mask lithography is well known in the art and is most commonly used in industries.
Double patterning technique utilizing self-aligned spacer is also known in the art. For example, a spacer layer is formed by deposition on the previous pattern, followed by etching to remove all the spacer layer material on the horizontal surfaces, leaving only the spacer layer material on the sidewalls. By removing the original patterned feature, only the spacer is left. Since there are two spacers for every line, the line density has now doubled. The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example. The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes.
However, the above-described double patterning technique utilizing self-aligned spacer has several drawbacks such as corner rounding or variation of the feature size across the wafer when using the spacer as an etching hard mask. In light of the above, there is a strong need in this industry to provide an improved method for fabricating a very fine pattern of semiconductor device with a feature size of at least 50 nm or below without the above-described drawbacks.